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RTL8201E-GR rtl8201el-gr rtl8201e-vb-gr rtl8201el-vb-gr single-chip/port 10/100 fast ethernet phyceiver with auto mdix datasheet (confidential: development partners only) rev. 1.3 16 december 2008 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix ii track id: jatr-1076-21 rev. 1.3 copyright ?2008 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the software engin eer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. revision history revision release date summary 1.0 2008/06/18 first release. 1.1 2008/08/08 revised table 19, page 15. added section 8.5 led and phy address configuration, page 21. revised section 8.11 3.3v power supply and voltage conversion circuit, page 25. added section 9.1.3 power on sequence, page 26. added section 9.1.4 phy reset sequence, page 27. revised table 32, page 28. 1.2 2008/11/14 removed rmii function. removed intb function. 1.3 2008/12/16 added rtl8201e(l)-vb-gr version and features (rmii and intb).
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix iii track id: jatr-1076-21 rev. 1.3 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. applications ................................................................................................................... .............................................2 4. block diagram .................................................................................................................. .........................................3 5. pin assignments ................................................................................................................ .........................................4 5.1. rtl8201el lqfp-48 p in a ssignments ...................................................................................................................4 5.2. g reen p ackage and v ersion i dentification ........................................................................................................4 5.3. rtl8201e qfn-32 p in a ssignments .......................................................................................................................5 5.4. g reen p ackage and v ersion i dentification ........................................................................................................5 6. pin descriptions............................................................................................................... ..........................................6 6.1. mii i nterface ............................................................................................................................... .............................6 6.2. rmii i nterface (rtl8201e(l)-vb o nly )..............................................................................................................8 6.3. sni (s erial n etwork i nterface ) 10m bps o nly ...................................................................................................8 6.4. c lock i nterface ............................................................................................................................... ........................8 6.5. 10m bps /100m bps n etwork i nterface ...................................................................................................................9 6.6. d evice c onfiguration i nterface ..........................................................................................................................9 6.7. led i nterface /phy a ddress c onfiguration ....................................................................................................10 6.8. p ower and g round p ins ............................................................................................................................... .........10 6.9. r eset and o ther p ins ............................................................................................................................... ..............10 6.10. nc (n ot c onnected ) p ins ............................................................................................................................... .......10 7. register descriptions.......................................................................................................... ...............................11 7.1. r egister 0 b asic m ode c ontrol r egister ..........................................................................................................11 7.2. r egister 1 b asic m ode s tatus r egister .............................................................................................................12 7.3. r egister 2 phy i dentifier r egister 1..................................................................................................................12 7.4. r egister 3 phy i dentifier r egister 2..................................................................................................................13 7.5. r egister 4 a uto -n egotiation a dvertisement r egister (anar) ...................................................................13 7.6. r egister 5 a uto -n egotiation l ink p artner a bility r egister (anlpar)....................................................14 7.7. r egister 6 a uto -n egotiation e xpansion r egister (aner) ............................................................................15 7.8. r egister 16 nw ay s etup r egister (nsr)............................................................................................................15 7.9. r egister 17 l oopback , b ypass , r eceiver e rror m ask r egister (lbremr).................................................15 7.10. r egister 18 rx_er c ounter (rec) .....................................................................................................................16 7.11. r egister 19 snr d isplay r egister ......................................................................................................................16 7.12. r egister 25 t est r egister ............................................................................................................................... ......16 8. functional description......................................................................................................... ............................17 8.1. mii and m anagement i nterface ..........................................................................................................................18 8.1.1. data tran sitio n ................................................................................................................ ....................................18 8.1.2. serial management.............................................................................................................. .................................19 8.1.3. interrupt (rtl8 201el-vb only).................................................................................................. ........................20 8.2. a uto -n egotiation and p arallel d etection .....................................................................................................20 8.2.1. setting the medium type and interface mode to mac.............................................................................. ...........20 8.3. f low c ontrol s upport ............................................................................................................................... ...........20 8.4. h ardware c onfiguration and a uto -n egotiation ...........................................................................................21 8.5. led and phy a ddress c onfiguration ...............................................................................................................21 8.6. s erial n etwork i nterface ............................................................................................................................... ....22 8.7. p ower d own , l ink d own , and p ower s aving m odes ........................................................................................22 8.8. m edia i nterface ............................................................................................................................... ......................23
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix iv track id: jatr-1076-21 rev. 1.3 8.8.1. 100base-tx transmit an d receive operation ...................................................................................... ...............23 8.8.2. 100base-fx fiber transmit and receive op eration ................................................................................ ...........23 8.8.3. 10base-t transmit and receive op eration........................................................................................ ..................24 8.9. r epeater m ode o peration ............................................................................................................................... .....24 8.10. r eset and t ransmit b ias ............................................................................................................................... ........24 8.11. 3.3v p ower s upply and v oltage c onversion c ircuit ......................................................................................25 8.12. f ar e nd f ault i ndication ............................................................................................................................... ......25 9. characteristics................................................................................................................ ......................................26 9.1. dc c haracteristics ............................................................................................................................... ................26 9.1.1. absolute maxi mum ratings ....................................................................................................... ...........................26 9.1.2. operating conditions ........................................................................................................... ................................26 9.1.3. power on sequence.............................................................................................................. ................................26 9.1.4. phy reset sequence............................................................................................................. ................................27 9.1.5. power dissi pation .............................................................................................................. ..................................27 9.1.6. input volta ge: vcc............................................................................................................. ...................................28 9.2. ac c haracteristics ............................................................................................................................... ................28 9.2.1. mii transmission cycle ti ming .................................................................................................. .........................28 9.2.2. mii reception cycle ti ming..................................................................................................... ............................30 9.2.3. rmii transmission cycle ti ming (rtl8201e(l)-vb only) ........................................................................... .....31 9.2.4. rmii reception cycle timi ng (rtl8201e(l )-vb only).............................................................................. ........31 9.2.5. sni transmission cycle timing .................................................................................................. .........................32 9.2.6. sni reception c ycle ti ming..................................................................................................... ............................33 9.2.7. mdc/mdio timing ................................................................................................................ .............................34 9.2.8. transmission w ithout collision ................................................................................................. ...........................34 9.2.9. reception with out error ........................................................................................................ ...............................35 9.3. c rystal c haracteristics ............................................................................................................................... ......35 9.4. t ransformer c haracteristics ............................................................................................................................35 10. mechanical dimensions.......................................................................................................... .......................36 10.1. rtl8201e 32-p in qfn ............................................................................................................................ ................36 10.2. rtl8201el 48-p in lqfp ........................................................................................................................... .............37 11. ordering information ........................................................................................................... ........................38
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix v track id: jatr-1076-21 rev. 1.3 list of tables t able 1. mii i nterface ............................................................................................................................... ...............................6 t able 2. rmii i nterface (rtl8201e(l)-vb o nly ) ................................................................................................................8 t able 3. sni (s erial n etwork i nterface ) 10m bps o nly ......................................................................................................8 t able 4. c lock i nterface ............................................................................................................................... ..........................8 t able 5. 10m bps /100m bps n etwork i nterface ......................................................................................................................9 t able 6. d evice c onfiguration i nterface .............................................................................................................................9 t able 7. led i nterface /phy a ddress c onfiguration ......................................................................................................10 t able 8. p ower and g round p ins ............................................................................................................................... ...........10 t able 9. r eset and o ther p ins ............................................................................................................................... ................10 t able 10. nc (n ot c onnected ) p ins ............................................................................................................................... .........10 t able 11. r egister 0 b asic m ode c ontrol r egister ............................................................................................................11 t able 12. r egister 1 b asic m ode s tatus r egister ...............................................................................................................12 t able 13. r egister 2 phy i dentifier r egister 1 ...................................................................................................................12 t able 14. r egister 3 phy i dentifier r egister 2 ...................................................................................................................13 t able 15. r egister 4 a uto -n egotiation a dvertisement r egister (anar) .....................................................................13 t able 16. r egister 5 a uto -n egotiation l ink p artner a bility r egister (anlpar)......................................................14 t able 17. r egister 6 a uto -n egotiation e xpansion r egister (aner) ..............................................................................15 t able 18. r egister 16 nw ay s etup r egister (nsr) .............................................................................................................15 t able 19. r egister 17 l oopback , b ypass , r eceiver e rror m ask r egister (lbremr)...................................................15 t able 20. r egister 18 rx_er c ounter (rec) .......................................................................................................................16 t able 21. r egister 19 snr d isplay r egister ........................................................................................................................16 t able 22. r egister 25 t est r egister ............................................................................................................................... ........16 t able 23. s erial m anagement ............................................................................................................................... .................19 t able 24. s etting the m edium t ype and i nterface m ode to mac....................................................................................20 t able 25. a uto -n egotiation m ode p in s ettings ..................................................................................................................21 t able 26. p ower s aving m ode p in s ettings ..........................................................................................................................22 t able 27. a bsolute m aximum r atings ............................................................................................................................... ...26 t able 28. o perating c onditions ............................................................................................................................... ..............26 t able 29. p ower o n s equence ............................................................................................................................... ..................26 t able 30. phy r eset s equence o perating c onditions ........................................................................................................27 t able 31. p ower d issipation ............................................................................................................................... .....................27 t able 32. i nput v oltage : v cc ............................................................................................................................... ..................28 t able 33. mii t ransmission c ycle t iming .............................................................................................................................28 t able 34. mii r eception c ycle t iming ............................................................................................................................... ....30 t able 35. rmii t ransmission c ycle t iming (rtl8201e(l)-vb o nly ) ...............................................................................31 t able 36. rmii r eception c ycle t iming (rtl8201e(l)-vb o nly ) .....................................................................................31 t able 37. sni t ransmission c ycle t iming .............................................................................................................................32 t able 38. sni r eception c ycle t iming ............................................................................................................................... ....33 t able 39. mdc/mdio t iming ............................................................................................................................... ....................34 t able 40. c rystal c haracteristics ............................................................................................................................... ........35 t able 41. t ransformer c haracteristics ..............................................................................................................................3 5 t able 42. o rdering i nformation ............................................................................................................................... .............38
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix vi track id: jatr-1076-21 rev. 1.3 list of figures f igure 1. b lock d iagram ............................................................................................................................... ...........................3 f igure 2. rtl8201el lqfp-48 p in a ssignments ....................................................................................................................4 f igure 3. rtl8201e qfn-32 p in a ssignment ..........................................................................................................................5 f igure 4. r ead c ycle ............................................................................................................................... ................................19 f igure 5. w rite c ycle ............................................................................................................................... ..............................19 f igure 6. led and phy a ddress c onfiguration ................................................................................................................21 f igure 7. p ower o n s equence ............................................................................................................................... .................26 f igure 8. phy r eset s equence ............................................................................................................................... ................27 f igure 9. mii t ransmission c ycle t iming -1.........................................................................................................................29 f igure 10. mii t ransmission c ycle t iming -2.........................................................................................................................29 f igure 11. mii r eception c ycle t iming -1 ............................................................................................................................. .30 f igure 12. mii r eception c ycle t iming -2 ............................................................................................................................. .30 f igure 13. rmii t ransmission c ycle t iming .........................................................................................................................31 f igure 14. rmii r eception c ycle t iming ............................................................................................................................... 31 f igure 15. sni t ransmission c ycle t iming -1 ........................................................................................................................32 f igure 16. sni t ransmission c ycle t iming -2 ........................................................................................................................32 f igure 17. sni r eception c ycle t iming -1 ............................................................................................................................. .33 f igure 18. sni r eception c ycle t iming -2 ............................................................................................................................. .33 f igure 19. mdc/mdio t iming ............................................................................................................................... ...................34 f igure 20. mac to phy t ransmission w ithout c ollision .................................................................................................34 f igure 21. phy to mac r eception w ithout e rror .............................................................................................................35
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 1 track id: jatr-1076-21 rev. 1.3 1. general description the rtl8201e(l) is a single-chip/single-por t fast ethernet phy ceiver that supports: ? mii (media independent interface) ? rmii (reduced media independent interface; rtl8201e(l)-vb only) ? sni (serial network interface) it implements all 10/100m ethernet physical-layer functions including the physical coding sublayer (pcs), physical medium attachme nt (pma), twisted pair physical medium dependent sublayer (tp- pmd), with an auto mdix function, 10base-tx enc oder/decoder, and twisted-pair media access unit (tpmau). a pecl (pseudo emitter coupled logic) interface is supported to connect with an external 100base-fx fiber optical transceiver. the chip utilizes an advanced cmos pro cess to meet low voltage and low power requirements. with on-chip dsp (digital signal processing ) technology, the chip provides excellent performance unde r all operating conditions.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 2 track id: jatr-1076-21 rev. 1.3 2. features ? supports mii and 7-wire sni (serial network interface) ? supports rmii mode (rtl8201e(l)-vb only) ? 10/100mbps operation ? full/half duplex operation ? twisted pair or fiber mode output ? auto-negotiation ? supports power down mode ? supports operation under link down power saving mode ? supports base line wander (blw) compensation ? supports auto mdix ? supports repeater mode ? supports interrupt function (rtl8201el- vb only) ? adaptive equalization ? network status leds ? flow control support ? 25mhz crystal/oscillator as clock source ? ieee 802.3/802.3u compliant ? low power supply, 1.2v, and 3.3v; 1.2v is generated by an internal regulator ? 0.11m cmos process ? 48-pin lqfp package (rtl8201el) ? 32-pin qfn package (rtl8201e) 3. applications ? network interface adapter ? mau (media access unit) ? cnr (communication and network riser) ? acr (advanced communication riser) ? ethernet hub ? ethernet switch in addition, it can be used in any embedded system with an ethernet mac that needs a utp physical connection or fiber pecl interface to an ex ternal 100base-fx optical transceiver module.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 3 track id: jatr-1076-21 rev. 1.3 4. block diagram rxin+ rxin- txo+ txo- rxc 25m txc txd rxd td+ variable current 3 level driver master ppl adaptive equalizer peak detect 3 level control voltage mlt-3 to nrzi serial to parrallel ck data slave pll parrallel to serial baseline wander correction data alignment descrambler scrambler 10/100 half/full switch logic 10/100m auto-negotiation control logic manchester coded waveform 10m output waveform shaping data recovery receive low pass filter rxd rxc 25m txd txc txd10 txc10 rxd10 rxc10 link pulse 10m 100 m sni interface mii interface 5b 4b decoder 4b 5b encoder 25m 25m 25m comparator rmii interface figure 1. block diagram
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 4 track id: jatr-1076-21 rev. 1.3 5. pin assignments 5.1. rtl8201el lqfp-48 pin assignments figure 2. rtl8201el lqfp-48 pin assignments 5.2. green package and version identification green package is indicated by a ?g? in the location ma rked ?t? in figure 2. the version is shown in the location marked ?v?.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 5 track id: jatr-1076-21 rev. 1.3 5.3. rtl8201e qfn-32 pin assignments figure 3. rtl8201e qfn-32 pin assignment 5.4. green package and version identification green package is indicated by a ?g? in the location ma rked ?t? in figure 3. the version is shown in the location marked ?v?.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 6 track id: jatr-1076-21 rev. 1.3 6. pin descriptions i: input li: latched input during power up or reset o: output io: bi-directional input and output p: power hz: high impedance during power on reset pu: internal pull up during power on reset pd: internal pull down during power on reset 6.1. mii interface table 1. mii interface name type pin no. (48-pin) pin no. (32-pin) description txc o/hz 22 15 transmit clock. this pin provides a continuous clock as a timing reference for txd[3:0] and txen. txen i/pd 27 20 transmit enable. the input signal indicates the presence of valid nibble data on txd[3:0]. an internal weakly pulled low resistor prevents the bus floating. txd[0:3] i/pd 23, 24, 25, 26 16, 17, 18, 19 transmit data. the mac will source txd[0:3] synchr onous with txc when txen is asserted. an internal weakly pulled low resistor prevents the bus floating. rxc o/hz 19 13 receive clock. this pin provides a continuous clock reference for rxdv and rxd[0:3] signals. rxc is 25mhz in 100mbps mode and 2.5mhz in 10mbps mode. col/sni li/o/pd 38 27 collision detect. col is asserted high when a collision is detected on the media. this pin?s status is latched at power on reset to determine at which interface mode to operate: 0: mii/rmii mode 1: sni mode this pin can be directly connected to gnd or vcc. note: only the rtl8201e(l)-vb supports rmii mode. crs/rptr/ crs_dv li/o/pd 36 26 carrier sense. this pin?s signal is asserted high if the media is not in idle state. at power on reset, this pin set high to put the rtl8201e(l) into repeater mode. this pin can be directly connected to gnd or vcc.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 7 track id: jatr-1076-21 rev. 1.3 name type pin no. (48-pin) pin no. (32-pin) description rxdv li/o/pd 13 8 receive data valid. this pin?s signal is asserted high when received data is present on the rxd[3:0] lines. the signal is de-assert ed at the end of the packet. the signal is valid on the rising edge of the rxc. this pin should be pulled low when operating in mii mode. 0: mii mode 1: rmii mode an internal weakly pulled low resistor sets this to the default of mii mode. it is possible to use an external 4.7k ? pulled high resistor to enable rmii mode. after power on, the pin operates as the receive data valid pin. note: only the rtl8201e(l)-vb supports rmii mode. rxd[0:3] o/pd 14, 16, 17, 18 9, 10, 11, 12 receive data. these are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the rxc for reception by the external physical unit (phy). rxer/fxen li/o/pd 39 28 receive error. if a 5b decode error occurs, such as invalid /j/k/, invalid /t/r/, or invalid symbol, this pin will go high. fiber/utp enable. this pin?s status is latched at power on reset to determine the media mode to operate in. 1: fiber mode 0: utp mode an internal weakly pulled low resistor sets this to the default of utp mode. it is possible to use an external 4.7k ? pulled high resistor to enable fiber mode. after power on, the pin operates as the receive error pin. mdc i/pu 30 22 management data clock. this pin provides a clock synchronous to mdio, which may be asynchronous to the transmit txc and receive rxc clocks. the clock rate can be up to 2.5mhz. use an internal weakly pulled high resistor to prevent the bus floating. mdio io/pu 31 23 management data input/output. this pin provides the bi-directional signal used to transfer management information.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 8 track id: jatr-1076-21 rev. 1.3 6.2. rmii interface (rtl8201e(l)-vb only) table 2. rmii interface (rtl8201e(l)-vb only) name type pin no. (48-pin) pin no. (32-pin) description txc io 22 15 synchronous 50mhz clock refere nce for receive, transmit, and control interface. the direction is decided by register 25. crs/rptr/ crs_dv o 36 26 carrier sense/receive data valid. crs_dv shall be asserted by the phy when the receive medium is non-idle. rxd[0:1] o 14, 16 9, 10 receive data. txen i 27 20 transmit enable. txd[0:1] i 23, 24 16, 17 transmit data. rxer/fxen o 39 28 receive error. 6.3. sni (serial network interface) 10mbps only table 3. sni (serial network interface) 10mbps only name type pin no. (48-pin) pin no. (32-pin) description col/sni o/pd 38 27 collision detect. rxd0 o/pd 14 9 received serial data. crs/rptr/ crs_dv o/pd 36 26 carrier sense. rxc o/hz 19 13 receive clock. resolved from received data. txd0 i/pd 23 16 transmit serial data. txc o/hz 22 15 transmit clock. generated by phy. txen i/pd 27 20 transmit enable. for mac to indicate transmit operation. 6.4. clock interface table 4. clock interface name type pin no. (48-pin) pin no. (32-pin) description ckxtal2 o 43 32 25mhz crystal output. this pin provides the 25mhz crystal output. it must be left open when an external 25mhz oscillator drives x1. ckxtal1 i 42 31 25mhz crystal input. this pin provides the 25mhz crysta l input. if a 25mhz oscillator is used, connect ckxtal1 to the oscillator?s output (see 9.3 crystal characteristics, page 35, for clock source specifications).
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 9 track id: jatr-1076-21 rev. 1.3 6.5. 10mbps/100mbps network interface table 5. 10mbps/100mbps network interface name type pin no. (48-pin) pin no. (32-pin) description mdi+[0] mdi-[0] o 1 2 3 4 transmit output. differential transmit output pair shared by 100base-tx, 100base- fx, and 10base-t modes. when configured as 100base-tx, output is an mlt-3 encoded waveform. when configured as 100base-fx, the output is pseudo-ecl level. rset i 46 1 transmit bias resistor connection. this pin should be pulled to gnd by a 2.49k ? (1%) resistor to define driving current for the tr ansmit dac. the resistance value may be changed, depending on experimental results of the rtl8201e(l). mdi+[1] mdi-[1] i 4 5 5 6 receive input. differential receive input pair sh ared by 100base-tx, 100base-fx, and 10base-t modes. 6.6. device configuration interface table 6. device configuration interface name type pin no. (48-pin) pin no. (32-pin) description rxdv li/o /pd 13 8 rmii/mii interface this pin?s status is latched at power on reset to determine at which interface mode to operate: 0: mii mode 1: rmii mode an internal weakly pulled low resistor sets this to the default mii mode. it is possible to use an external 4.7k ? pulled high resistor to enable rmii mode. note: only the rtl8201e(l)-vb supports rmii mode. led0/phyad[0] led1/phyad[1] li/o /hz 34 35 24 25 phy address. sets the phy address for the device. crs/rptr/ crs_dv li/o /pd 36 26 repeater mode. set high to put the rtl8201e(l) into repeater mode. this pin can be directly connected to gnd or vcc. col/sni li/o /pd 38 27 mii/rmii/sni interface. this pin is latched to input at a power on or reset condition. pull high to set the rtl8201e(l) into sni mode operation. set low for mii/rmii mode. this pin can be directly connected to gnd or vcc. note: only the rtl8201e(l)-vb supports rmii mode. rxer/fxen li/o /pd 39 28 fiber/utp interface. this pin?s status is latched at power on reset to determine the media mode to operate in. 1: fiber mode 0: utp mode an internal weakly pulled low resistor sets this to the default of utp mode. it is possible to use an external 4.7k ? pulled high resistor to enable fiber mode.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 10 track id: jatr-1076-21 rev. 1.3 6.7. led interface/phy address configuration table 7. led interface/phy address configuration name type pin no. (48-pin) pin no. (32-pin) description led0/phyad[0] li/o/hz 34 24 link indicator. led1/phyad[1] li/o/hz 35 25 receive/transmit led. 6.8. power and ground pins table 8. power and ground pins name type pin no. (48-pin) pin no. (32-pin) description avdd33 p 6, 41 7, 30 3.3v analog power input. 3.3v power supply for analog circuit; should be well decoupled. dvdd33 p 15, 21, 37 14 3.3v digital power input. 3.3v power supply for digital circuit. dvdd12 p 28 - 1.2v digital power. gnd p 7, 20, 33, 47 - ground. should be connected to a larger gnd plane. 6.9. reset and other pins table 9. reset and other pins name type pin no. (48-pin) pin no. (32-pin) description phyrstb i/hz 29 21 resetb. set low to reset the chip. for a complete reset, this pin must be asserted low for at least 10ms. pwout12d pwout12a o 40 48 29 2 power output. be sure to connect a 0.1f ceramic capacitor for decoupling purposes. the connection method is outlined in 8.11 3.3v power supply and voltage conversion circuit, page 25. intb o 32 - interrupt. set low if link status change, duplex change and auto negotiation fail, active low. note: only the rtl8201el-vb supports interrupt pin. 6.10. nc (not connected) pins table 10. nc (not connected) pins name type pin no. (48-pin) pin no. (32-pin) description nc - 3, 8, 9, 10, 11, 12, 32, 44, 45 (pin 32 is nc in rtl8201el-gr only) - not connected.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 11 track id: jatr-1076-21 rev. 1.3 7. register descriptions this section describes the func tions and usage of the register s available in the rtl8201e(l). in this section the following abbreviations are used: ro: read only rw: read/write 7.1. register 0 basic mode control register table 11. register 0 basic mode control register address name description mode default 0:15 reset this bit sets the status and control registers of the phy in the default state. this bit is self-clearing. 1: software reset 0: normal operation rw 0 0:14 loopback this bit enables loopback of transmit data nibbles txd3:0 to the receive data path. 1: enable loopback 0: normal operation rw 0 0:13 spd_set this bit sets the network speed. 1: 100mbps 0: 10mbps after completing auto negotiation, this bit will reflect the speed status. 1: 100base-t 0: 10base-t when 100base-fx mode is enabled, this bit=1 and is read only. rw 0 0:12 auto negotiation enable this bit enables/disables the nway auto-negotiation function. 1: enable auto-negotiation; bits 0:13 and 0:8 will be ignored 0: disable auto-negotiation; bits 0:13 and 0:8 will determine the link speed and the data transfer mode, respectively when 100base-fx mode is enabled, this bit=0 and is read only. rw 1 0:11 power down this bit turns down the power of the phy chip, including the internal crystal oscillator circuit. the mdc, mdio is still a live for accessing the mac. 1: power down 0: normal operation rw 0 0:10 reserved reserved. - - 0:9 restart auto negotiation this bit allows the nway auto-negotiation function to be reset. 1: re-start auto-negotiation 0: normal operation rw 0 0:8 duplex mode this bit sets the duplex mode if auto-negotiation is disabled (bit 0:12=0). 1: full duplex 0: half duplex after completing auto-negotiation, this bit will reflect the duplex status. 1: full duplex 0: half duplex rw 0 0:7~0 reserved reserved. - -
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 12 track id: jatr-1076-21 rev. 1.3 7.2. register 1 basic mode status register table 12. register 1 basic mode status register address name description mode default 1:15 100base-t4 1: enable 100base-t4 support 0: suppress 100base-t4 support ro 0 1:14 100base_tx_ fd 1: enable 100base-tx full duplex support 0: suppress 100base-tx full duplex support ro 1 1:13 100base_tx_hd 1: enable 100base-tx half duplex support 0: suppress 100base-tx half duplex support ro 1 1:12 10base_t_fd 1: enable 10base-t full duplex support 0: suppress 10base-t full duplex support ro 1 1:11 10_base_t_hd 1: enable 10base-t half duplex support 0: suppress 10base-t half duplex support ro 1 1:10~7 reserved reserved. - - 1:6 mf preamble suppression the rtl8201e(l) will accept management frames with preamble suppressed. a minimum of 32 preamble bits are required for the first smi read/write transaction after reset. one idle bit is required between any two management transactions as per ieee 802.3u specifications. ro 1 1:5 auto negotiation complete 1: auto-negotiation process completed 0: auto-negotiation process not completed ro 0 1:4 remote fault 1: remote fault condition detected (cleared on read) 0: no remote fault condition detected when in 100base-fx mode, this bit means an in-band signal far-end-fault has been detected (see 8.12 far end fault indication, page 25). ro 0 1:3 reserved reserved. - - 1:2 link status 1: valid link established 0: no valid link established ro 0 1:1~0 reserved reserved. - - 7.3. register 2 phy identifier register 1 table 13. register 2 phy identifier register 1 address name description mode default 2:15~0 oui_msb organizationally unique identifier bit 3:18 ro 001ch
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 13 track id: jatr-1076-21 rev. 1.3 7.4. register 3 phy identifier register 2 table 14. register 3 phy identifier register 2 address name description mode default 3:15~10 oui_lsb organizationally unique identifier bit 19:24 ro 110010 3:9~4 model number model number ro 000001 3:3~0 revision number revision number ro 0101 7.5. register 4 auto-negotiation advertisement register (anar) this register contains the advertised abilities of this device as they wi ll be transmitted to its link partner during auto-negotiation. table 15. register 4 auto-negotia tion advertisement register (anar) address name description mode default 4:15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page ro 0 4:14 ack 1: acknowledge reception of link partner capability data word 0: do not acknowledge reception ro 0 4:13 rf 1: advertise remote fault detection capability 0: do not advertise remote fault detection capability rw 0 4:12~11 reserved reserved. - - 4:10 rxfc 1: rx flow control is supported by local node 0: rx flow control not supported by local node rw 0 4:9 t4 1: 100base-t4 is supported by local node 0: 100base-t4 not supported by local node ro 0 4:8 txfd 1: 100base-tx full duplex is supported by local node 0: 100base-tx full duplex not supported by local node rw 1 4:7 tx 1: 100base-tx is supported by local node 0: 100base-tx not supported by local node rw 1 4:6 10fd 1: 10base-t full duplex supported by local node 0: 10base-t full duplex not supported by local node rw 1 4:5 10 1: 10base-t is supported by local node 0: 10base-t not supported by local node rw 1 4:4~0 selector binary encoded selector supported by this node. currently only csma/cd 00001 is specified. no other protocols are supported. rw 00001
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 14 track id: jatr-1076-21 rev. 1.3 7.6. register 5 auto-negotiation link partner ability register (anlpar) this register contains the advertised abilities of th e link partner as received dur ing auto-negotiation. the content changes after a successful auto-n egotiation if next-p ages are supported. table 16. register 5 auto -negotiation link partner ability register (anlpar) address name description mode default 5:15 np next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page ro 0 5:14 ack 1: link partner acknowledges reception of local node?s capability data word 0: no acknowledgement ro 0 5:13 rf 1: link partner is indicating a remote fault 0: link partner is not indicating a remote fault ro 0 5:12 reserved reserved. - - 5:11 txfc 1: tx flow control is supported by link partner 0: tx flow control not supported by link partner ro 0 5:10 rxfc 1: rx flow control is supported by link partner 0: rx flow control not supported by link partner ro 0 5:9 t4 1: 100base-t4 is supported by link partner 0: 100base-t4 not supported by link partner ro 0 5:8 txfd 1: 100base-tx full duplex is supported by link partner 0: 100base-tx full duplex not supported by link partner ro 0 5:7 100base-tx 1: 100base-tx is supported by link partner 0: 100base-tx not supported by link partner this bit will also be set if the link in 100base is established by parallel detection. ro 0 5:6 10fd 1: 10base-t full duplex is supported by link partner 0: 10base-t full duplex not supported by link partner ro 0 5:5 10base-t 1: 10base-t is supported by link partner 0: 10base-t not supported by link partner this bit will also be set if the link in 10base-t is established by parallel detection. ro 0 5:4~0 selector link partner?s binary encoded node selector. currently only csma/cd 00001 is specified. ro 00000
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 15 track id: jatr-1076-21 rev. 1.3 7.7. register 6 auto-negotiation expansion register (aner) this register contains additional status for nway auto-negotiation. table 17. register 6 auto-negotiation expansion register (aner) address name description mode default 6:15~5 reserved reserved. - - 6:4 mlf indicates whether a multiple link fault has occurred. 1: fault occurred 0: no fault occurred ro 0 6:3 lp_np_able indicates whether the link partner supports next page negotiation. 1: supported 0: not supported ro 0 6:2 np_able this bit indicates whether the local node is able to send additional next pages. internal use only. ro 0 6:1 page_rx this bit is set when a new li nk code word page has been received. it is automatically cleared when the auto-negotiation link partner?s ability register (register 5) is read by management. ro 0 6:0 lp_nw_able 1: link partner supports nway auto-negotiation. ro 0 7.8. register 16 nway setup register (nsr) table 18. register 16 nway setup register (nsr) address name description mode default 16:15~11 reserved realtek test mode internal use. do not change this field without realtek?s approval. - - 16:10 testfun 1: auto-negotiation speeds up internal timer rw 0 16:9 nwlpbk 1: set nway to loopback mode rw 0 16:8~3 reserved reserved. - - 16:2 flagabd 1: auto-negotiation experienced ability detect state ro 0 16:1 flagpdf 1: auto-negotiation experienced parallel detection fault state ro 0 16:0 flaglsc 1: auto-negotiation experienced link status check state ro 0 7.9. register 17 loopback, bypass, receiver error mask register (lbremr) table 19. register 17 loopback, bypass, receiver error mask register (lbremr) address name description mode default 17:15 rptr set to 1 to put the rtl8201e(l) into repeater mode. rw 0 17:14 bp_4b5b assertion of this bit allows bypassing of the 4b/5b & 5b/4b encoder. rw 0 17:13 bp_scr assertion of this bit allows bypassing of the scrambler/descrambler. rw 0 17:12 ldps set to 1 to enable link down power saving mode. rw 0 17:11 analogoff set to 1 to power down the an alog function of transmitter and receiver. rw 0 17:10 bmode_en sets the inverse functio n of the receive/transmit led. rw 1 17:9 lb set to 1 to enable dsp loopback. rw 0 17:8 f_link_10 used to logic force a good link in 10mbps for diagnostic purposes. rw 1
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 16 track id: jatr-1076-21 rev. 1.3 address name description mode default 17:7 f_link_100 used to logic force a good link in 100mbps for diagnostic purposes. rw 1 17:6 jben set to 1 to enable jabber function in 10base-t. rw 1 17:5 code_err assertion of this bit causes a code error detection to be reported. rw 0 17:4 pme_err assertion of this bit causes a pre-mature end error detection to be reported. rw 0 17:3 link_err assertion of this bit causes a link error detection to be reported. rw 0 17:2 pkt_err assertion of this bit causes a ?detectio n of packet errors due to 722 ms time-out? to be reported. rw 0 17:1 fxmode this bit indicates whether fiber mode is enabled. rw 0 17:0 snimode this bit indicates whether sni mode is enabled. rw 0 7.10. register 18 rx_er counter (rec) table 20. register 18 rx_er counter (rec) address name description mode default 18:15~0 rxercnt this 16-bit counter increments by 1 for each invalid packet received. the value is valid while the link is established. ro 0000 7.11. register 19 snr display register table 21. register 19 snr display register address name description mode default 19:15~4 reserved realtek test mode internal use. do not change this field without realtek?s approval. - - 19:3~0 snr_0 these 4-bits show the signal to noise ratio value. rw 0000 7.12. register 25 test register table 22. register 25 test register address name description mode default 25:15~12 test reserved for internal testing. rw - 25:11 rmii_clkin this bit decides the type of txc in rmii mode 0: output 1: input rw 1 25:10 rmii mode this bit sets the rmii mode. 1: rmii mode 0: mii mode rw 0 25:9 reserved reserved. - - 25:7~8 phyad[1:0] reflects the phy address define d by external phy address configuration pins. ro 00001 25:6~2 test reserved for internal testing. ro - 25:1 link10 1: 10base-t link established 0: no 10base-t link established ro 0 25:0 link100 1: 100base-fx or 100base-tx link established 0: no 100base link established ro 0
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 17 track id: jatr-1076-21 rev. 1.3 8. functional description the rtl8201e(l) phyceiver is a physical laye r device that inte grates 10base-t and 100base-tx/100base-fx functions, and some extra pow er management features . this device supports the following functions: ? mii interface with mdc/mdio smi management interface to communicate with the mac ? ieee 802.3u clause 28 auto-negotiation ability ? flow control ability suppor t to cooperate with mac ? speed, duplex, auto-negotiati on ability configurable by hard wire or mdc/mdio ? flexible led configuration ? 7-wire sni (serial network interf ace) support (only in 10mbps mode) ? power down mode support ? 4b/5b transform ? scrambling/de-scrambling ? nrz to nrzi, nrzi to mlt-3 ? manchester encode and d ecode for 10base-t operation ? clock and data recovery ? adaptive equalization ? far end fault indication (fefi) in fiber mode
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 18 track id: jatr-1076-21 rev. 1.3 8.1. mii and management interface 8.1.1. data transition to set the rtl8201e(l) for mii mode operation, pull the col/sni pin low. the mii (media independent interf ace) is an 18-signal interface (as described in ieee 802.3u) supplying a standard interface between the phy and mac layer. this interface operates at two frequencies ? 25mhz and 2.5mhz ? to support 100mbps/10mbps bandwidth for both transmit and receive functions. transmission the mac asserts the txen signal. it then changes byt e data into 4-bit nibbles and passes them to the phy via txd[3:0]. the phy will sample txd[3:0] s ynchronously with txc ? the transmit clock signal supplied by phy ? during the interval txen is asserted. reception the phy asserts the rxen signal. it passes the re ceived nibble data rxd[3:0] clocked by rxc. crs and col signals are used for co llision detection and handling. in 100base-tx mode, when the decode d signal in 5b is not idle, the crs signal will assert. when 5b is recognized as idle it will be de-asserted. in 10bas e-t mode, crs will assert when the 10m preamble has been confirmed and will be de-asserted when the idle pattern has been confirmed. the rxdv signal will be asserted when decoded 5b are /j/k/ and will be de-asserted if the 5b are /t/r/ or idle in 100mbps mode. in 10mbps mode, the rxdv signal is the same as the crs signal. the rxer (receive error) signa l will be asserted if a ny 5b decode errors occur, e.g., an invalid j/k, invalid t/r, or invalid symbol. this pin will go high for one or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. note: the rtl8201e(l) does not use a txer signal. this does not affect the transmit function.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 19 track id: jatr-1076-21 rev. 1.3 8.1.2. serial management the mac layer device can use the mdc/mdio mana gement interface to control a maximum of 4 rtl8201e(l) devices, configured with different phy addresses (00b to 11b). during a hardware reset, the logic levels of pins 34/24 and 35/25 are latched in to the rtl8201e(l) to be set as the phy address for manageme nt communication via the serial in terface. the read and write frame structure for the management interface is illustrated in figure 4 and figure 5. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 0 1 1 0 0 32 1s op st preamble phyad[4:0] ta data regad[4:0] idle mdc mdio mdio is sourced by mac. clock data into phy on rising edge of mdc z mdio is sourced by phy. clock data from phy on rising edge of mdc figure 4. read cycle d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 1 0 1 0 1 0 32 1s op st preamble phyad[4:0] ta data regad[4:0] idle mdc mdio mdio is sourced by mac. clock data into phy on rising edge of mdc figure 5. write cycle table 23. serial management name description preamble 32 contiguous logical 1?s sent by the mac on mdio along with 32 corresponding cycles on mdc. this provides synchronization for the phy. st start of frame. indicated by a 01 pattern. op operation code. read: 10 write: 01 phyad phy address. up to 4 phys can be connected to one mac. this 2-bit field selects wh ich phy the frame is directed to. regad register address. this is a 5-bit field that sets which of the 32 registers of the phy th is operation refers to. ta turnaround. this is a 2-bit-time spacing between the register addr ess and the data field of a frame to avoid contention during a read transaction. for a read transaction, both the sta and the phy remain in a high-impedance state for the first bit time of the turnaround. the phy drives a zero bit during the second bit time of the turnaround of a read transaction. data data. these are the 16 bits of data. idle idle condition. not truly part of the management frame. this is a high impedance state. electrically, the phy?s pull-up resistor will pull the mdio line to a logical ?1?.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 20 track id: jatr-1076-21 rev. 1.3 8.1.3. interrupt (rtl8201el-vb only) whenever there is a status change on the media that the rtl8201el-vb detected, the rtl8201el-vb will drive the interrupt pin (intb) low to issue an inte rrupt event. the mac senses the status change and accesses the registers through the md c/mdio interface in response. once these status registers have been read by ma c through the mdc/mdio, the intb is de-asserted. the rtl8201el-vb interrupt f unction removes the need for continuous polling through the mdc/mdio manage ment interface. 8.2. auto-negotiation and parallel detection the rtl8201e(l) supports ieee 802.3u clause 28 auto-n egotiation for operation with other transceivers supporting auto-negotiation. the rtl 8201e(l) can auto-detect the link pa rtner?s abilities and determine the highest speed/duplex configurat ion possible between the two device s. if the link partner does not support auto-negotiation, then the rtl8201e(l) will enable half duplex mode and enter parallel detection mode. the rtl8201e(l) will default to tr ansmitting flp (fast link pulse) and wait for the link partner to respond. if the rtl8201e (l) receives a flp, then the auto-negotiation process will go on. if it receives nlp (normal link pulse), then the rtl8201e(l) will change to 10mbps and half duplex mode. if it receives a 100mbps idle pattern, it will change to 100mbps and half duplex mode. 8.2.1. setting the medium type a nd interface mode to mac table 24. setting the medium type and interface mode to mac fxen col/sni rxdv operation mode h l l fiber mode and mii mode. h l h fiber mode and rmii mode. h h x fiber mode and sni mode. l l l utp mode and mii mode. l l h utp mode and rmii mode. l h x utp mode and sni mode. 8.3. flow control support the rtl8201e(l) supports flow cont rol indications. the mac can progra m the mii register to indicate to the phy that flow control is supported. when th e mac supports the flow c ontrol mechanism, setting bit 10 of the anar register using the mdc/mdio sni interface, then the rtl8201e(l) will add the ability to its nway ability. if the link partner al so supports flow control, then the rtl8201e(l) can recognize the link partner?s nway ability by examining bit 10 of anlpar (register 5).
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 21 track id: jatr-1076-21 rev. 1.3 8.4. hardware configuration and auto-negotiation this section describes methods to configure the rtl8201e(l) and se t the auto-negotiation mode. table 25 shows the various pins and their settings. table 25. auto-negotiation mode pin settings pin name description crs/rptr/ crs_dv pull high to set the rtl8201e(l) into repeater mode. this pin is pulled low by default (see 8.9 repeater mode operation, page 24). col/sni pull low to set the rtl8201e(l) into mii/rmii mode operation, which is the default mode for the rtl8201e(l). this pin pulled high will set the rtl8201 e(l) into sni mode operation. when set to sni mode, the rtl8201e(l) will operate at 10mbps (see section 8.6 serial network interface, page 22). 8.5. led and phy address configuration in order to reduce the pin count on the rtl8201e(l), the led pins are duplexed with the phy address pins. the external combinations re quired for strapping and led usage mu st be considered in order to avoid contention. specifically, when the led outputs ar e used to drive leds dir ectly, the active state of each output driver is dependent on the logic level sampled by the corresponding phyad input upon power-up/reset. for example, as figu re 6 (left-side) shows, if a give n phyad input is resistively pulled high, then the corresponding out put will be configured as an active low driver. on the right side, we can see that if a given phyad input is resistively pulled low then the corresponding output will be configured as an active high driver. the phy address configuration pins should not be connected to gnd or vcc directly, but must be pulled high or low through a resistor (e.g., 4.7k ? ). if no led indications are needed, the components of the led path (led+510 ? ) can be removed. phy address[:]=logical 1 phy address[:]=logical 0 led indication=active low led indication=active high figure 6. led and phy address configuration
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 22 track id: jatr-1076-21 rev. 1.3 8.6. serial network interface the rtl8201e(l) also supports the traditional 7-wire serial interface to operate with legacy macs or embedded systems. to setup for this mode of oper ation, pull the col/sni pin high. in this mode, the rtl8201e(l) will set the default operation to 10mbps a nd half-duplex mode. this interface consists of a 10mbps transmit and receive clock generated by phy, 10 mbps transmit and receive serial data, transmit enable, collision detect, and carry sense signals. 8.7. power down, link down, and power saving modes three types of power saving mode operation are suppor ted. this section describes how to implement each mode through software. table 26. power saving mode pin settings mode description analog off setting bit 11 of register 17 to 1 will put the rtl8201e (l) into analog off state. in analog off state, the rtl8201e(l) will power down all analog functions such as transmit, receive, pll, etc. however, the internal 25mhz crystal oscillator will not be powere d down. digital functions in this mode are still available which allows reacqui sition of analog functions ldps setting bit 12 of register 17 to 1 will put the rtl8 201e(l) into ldps (link down power saving) mode. in ldps mode, the rtl8201e(l) will detect the link status to decide whether or not to turn off the transmit function. if the link is off, flp or 100mbps idle/10mbps nlp will not be transmitted. however, some signals similar to nlp will be transmitted. once the r eceiver detects leveled signals, it will stop the signal and transmit flp or 100mbps id le/10mbps nlp again. this can cut power used by 60%~80% when the link is down. pwd setting bit 11 of register 0 to 1 puts the rtl8201e(l) into power down mode. this is the maximum power saving mode while the rtl8201e(l) is still a live. in pwd mode, the rtl8201e(l) will turn off all analog/digital functions except the mdc/md io management interface. therefore, if the rtl8201e(l) is put into pwd mode and the mac wants to recall the phy, it must create the mdc/mdio timing by itself (this is done by software).
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 23 track id: jatr-1076-21 rev. 1.3 8.8. media interface 8.8.1. 100base-tx transmit and receive operation 100base-tx transmit transmit data in 4-bit nibbles (txd[3:0]) clocked at 25mhz (txc) is transformed into 5b symbol code (4b/5b encoding). scrambling, seri alizing, and conversion to 125mhz, and nrz to nrzi then takes place. after this process, the nrzi signal is passed to the mlt-3 encoder, then to the transmit line driver. the transmitter will first assert txen. before transm itting the data pattern, it will send a /j/k/ symbol (start-of-frame delimiter), the data symbol, and finally a /t/r/ symbol known as the end-of-frame delimiter. for better emi performance, the seed of the scrambler is based on the phy address. in a hub/switch environment, each rtl8201e(l) will have di fferent scrambler seeds and so spread the output of the mlt-3 signals. 100base-tx receive the received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and inter symbol interference (isi). ba seline wander correction mo nitors the process and dynamically applies corrections to the process of signal equalization. the phase locked loop (pll) then recovers the timing information from the signals and fr om the receive clock. with this, the received signal is sampled to form nrzi (non-return-to-zero invert ed) data. the next steps are the nrzi to nrz (non- return-to-zero) process, unscrambling of the data, seri al to parallel and 5b to 4b conversion, and passing of the 4b nibble to the mii interface. 8.8.2. 100base-fx fiber transmit and receive operation the rtl8201e(l) can be configured to 100base-fx mode via hardwa re configuration. the hardware 100base-fx setting takes priority over nway settings. a scrambler is not required in 100base-fx. 100base-fx transmit di-bits of txd are processed as 100base-tx except wi thout a scrambler before the nrzi stage. instead of converting to mlt-3 signals, as in 100base-tx, the serial data stream is driven out as nrzi pecl signals, which enter the fiber transc eiver in differential-pair form. 100base-fx receive the signal is received through pecl receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. th e scrambler/de-scrambler is bypassed in 100base-fx.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 24 track id: jatr-1076-21 rev. 1.3 8.8.3. 10base-t transmit and receive operation 10base-t transmit transmit data in 4-bit nibbles (txd[ 3:0]) clocked at 2.5mhz (txc) is fi rst fed to a parallel-to-serial converter, then the 10mbps nrz si gnal is sent to a manchester en coder. the manchester encoder converts the 10mbps nrz data into a manchester enc oded data stream for the tp transmitter and adds a start of idle pulse (soi) at the end of the packet as specified in ieee 802.3. fi nally, the encoded data stream is shaped by a band-limited filter embe dded in the rtl8201e(l) and then transmitted. 10base-t receive in 10base-t receive mode, the ma nchester decoder in the rtl8 201e(l) converts the manchester encoded data stream into nrz data by decoding the da ta and stripping off the so i pulse. then the serial nrz data stream is converted to a pa rallel 4-bit nibble signal (rxd[0:3]). 8.9. repeater mode operation setting bit 15 of register 17 to 1, or pulling the rptr pin high, sets th e rtl8201e(l) into repeater mode. in repeater mode, the rtl8201e(l) will assert crs hi gh only when receiving a packet. in nic mode, the rtl8201e(l) will assert crs high both when tran smitting and receiving packets. if using the rtl8201e(l) in a nic or switch application, set to the default mode. nic/switc h mode is the default setting and has the rptr pin pulled low, or bit 15 of register 17 is set to 0. 8.10. reset and transmit bias the rtl8201e(l) can be reset by pulling the phyrstb pin low for a bout 10ms, then pulling the pin high. it can also be reset by setting b it 15 of register 0 to 1, and then se tting it back to 0. reset will clear the registers and re-initialize them. the media interface will di sconnect and restart the auto- negotiation/parallel detection process. the rset pin must be pulled low by a 2.49k ? resister with 1% accuracy to establish an accurate transmit bias. this will affect the signal quality of the transmit wavefo rm. keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 25 track id: jatr-1076-21 rev. 1.3 8.11. 3.3v power supply and voltage conversion circuit the rtl8201e(l) is fabricated in a 0.11m process. the core circ uit needs to be powered by 1.2v, however, the digital io and dac ci rcuits need a 3.3v power supply. regulators are embedded in the rtl8201e(l) to convert 3.3v to 1.2v. an external 1.2v power supply is not suggested, as the internal regulators cannot be disabled, a nd two 1.2v power sources may conf lict. as with many commercial voltage conversion devices, the 1.2v output pin (pwfbout) of this circui t requires the use of an output capacitor (0.1f ceramic capacitor is recommended) as part of the device frequency compensation. the analog and digital ground planes should be as large and intact as possible. if the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. however, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. in this case, all the ground pins can be connected together to a larger single and intact ground plane. 8.12. far end fault indication the mii reg.1.4 (remote fault) is the far end fault indication (fefi) bit when 100fx m ode is enabled, and indicates when a fefi has been detected. fefi is an alternativ e in-band signaling method which is composed of 84 consecutive ?1?s followed by one ?0?. when the rtl8201e(l) det ects this pattern three times, reg.1.4 is set, which means the transmit path (t he remote side?s receiv e path) has a problem. on the other hand, if an incoming signal fails to cause a ?link ok?, the rtl8201e(l) will start sending this pattern, which in turn causes the remote side to detect a far end fault. this means that the receive path has a problem from the point of view of the rtl8201e(l). the fe fi mechanism is used only in 100base-fx mode.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 26 track id: jatr-1076-21 rev. 1.3 9. characteristics 9.1. dc characteristics 9.1.1. absolute maximum ratings table 27. absolute maximum ratings item minimum typical maximum supply voltage 2.97v 3.3v 3.63v storage temperature -55 c - 125 c 9.1.2. operating conditions table 28. operating conditions item condition minimum typical maximum vcc 3.3v 3.3v supply voltage 2.97v 3.3v 3.63v t a ambient operating temperature 0 c - 70 c 9.1.3. power on sequence figure 7. power on sequence table 29. power on sequence symbol description minimum maximum rt1 3.3v rise time 1ms 50ms rt2 1.2v delay time 300s 1ms the rtl8201e(l) needs 250ms power on time. afte r 250ms it can access the phy register from mdc/mdio.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 27 track id: jatr-1076-21 rev. 1.3 9.1.4. phy reset sequence figure 8. phy reset sequence table 30. phy reset sequence operating conditions symbol description minimum maximum rt1 3.3v rise time (phyrst) 1ms 10ms rt2 1.2v delay time 300s 1ms 9.1.5. power dissipation test condition: the data was measured from an rtl8201el de mo board. the total current consumption is defined as the system curre nt consumption, includi ng avdd3.3, dvdd3.3, avdd1.2, and dvdd1.2v power consumption, as well as regulator loss. table 31. power dissipation symbol condition total current consumption p ldps link down power saving mode 27ma p anaoff analog off mode 20ma p pwd power down mode 15ma p 100f 100base full duplex 62ma p 10f 10base-t full duplex 67ma p 10tx 10base-t transmit 66ma p 10rx 10base-t receive 29ma p 10idle 10base-t idle 27ma
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 28 track id: jatr-1076-21 rev. 1.3 9.1.6. input voltage: vcc table 32. input voltage: vcc symbol condition minimum maximum ttl v ih input high voltage - 0.5*vcc vcc +0.5v ttl v il input low voltage - -0.5v 0.7v ttl v oh output high voltage ioh=-8ma 0.65*vcc vcc ttl v ol output low voltage iol=8ma - 0.7v ttl i oz tri-state leakage vout=vcc or gnd -110a 10a i in input current vin=vcc or gnd -1a 10a i pl input current with internal weakly pulled low resistor vin=vcc or gnd -1a 100a i ph input current with internal weakly pulled high resistor vin=vcc or gnd -110a 10a pecl v ih pecl input high voltage - vdd -1.16v vdd -0.88v pecl v il pecl input low voltage - vdd -1.81v vdd -1.47v pecl v oh pecl output high voltage - vdd -1.02v - pecl v ol pecl output low voltage - - vdd -1.62v 9.2. ac characteristics 9.2.1. mii transmission cycle timing table 33. mii transmission cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 txclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 txclk low pulse width 10mbps 140 200 260 ns 100mbps - 40 - ns t 3 txclk period 10mbps - 400 - ns 100mbps 10 - - ns t 4 txen, txd[0:3] setup to txclk rising edge 10mbps 5 - - ns 100mbps 0 - 25 ns t 5 txen, txd[0:3] hold after txclk rising edge 10mbps 0 - - ns 100mbps - - 40 ns t 6 txen sampled to crs high 10mbps - - 400 ns 100mbps - - 160 ns t 7 txen sampled to crs low 10mbps - - 2000 ns 100mbps 60 70 140 ns t 8 transmit latency 10mbps - - 2000 ns 100mbps - 100 170 ns t 9 sampled txen inactiv e to end of frame 10mbps - - - ns
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 29 track id: jatr-1076-21 rev. 1.3 figure 9 and figure 10 and show an example of a pack et transfer from mac to phy on the mii interface. txclk v ih(min) v il(max) txd[0:3] txen v ih(min) v il(max) t 4 t 5 t 3 t 1 t 2 figure 9. mii transmission cycle timing-1 txclk txen txd[0:3] crs tptx+- t 6 t 8 t t 9 7 figure 10. mii transmission cycle timing-2
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 30 track id: jatr-1076-21 rev. 1.3 9.2.2. mii reception cycle timing table 34. mii reception cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 rxclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 rxclk low pulse width 10mbps 140 200 260 ns 100mbps - 40 - ns t 3 rxclk period 10mbps - 400 - ns 100mbps 10 - - ns t 4 rxer, rxdv, rxd[0:3] setup to rxclk rising edge 10mbps 10 - - ns 100mbps 10 - - ns t 5 rxer, rxdv, rxd[0:3] hold after rxclk rising edge 10mbps 10 - - ns 100mbps - - 130 ns t 6 receive frame to crs high 10mbps - - 2000 ns 100mbps - - 240 ns t 7 end of receive frame to crs low 10mbps - - 1000 ns 100mbps - - 150 ns t 8 receive frame to sampled edge of rxdv 10mbps - - 3200 ns 100mbps - - 120 ns t 9 end of receive frame to sampled edge of rxdv 10mbps - - 1000 ns figure 11 and figure 12 show an example of a packet transfer from phy to mac on the mii interface. rxclk rxd[0:3] rxdv rxer v ih(min) v il(max) v ih(min) v il(max) t 4 t 5 t 1 t 3 t 2 figure 11. mii reception cycle timing-1 rxclk rxdv rxd[0:3] crs tprx+- t 8 t 6 t 7 t 9 figure 12. mii reception cycle timing-2
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 31 track id: jatr-1076-21 rev. 1.3 9.2.3. rmii transmission cycle timi ng (rtl8201e(l)-vb only) table 35. rmii transmission cycl e timing (rtl8201e(l)-vb only) symbol description minimum typical maximum unit ref_clk frequency frequency of reference clock - 50 - mhz ref_clk duty cycle duty cycle of reference clock 35 - 65 % t_ipsu_txd_rmii txd/txen setup time to refclk 4 - - ns t_iphd_txd_rmii txd/txen hold time from refclk 2 - - ns valid data refclk txd t_ipsu_txd_rmii t_iphd_txd_rmii figure 13. rmii transmission cycle timing 9.2.4. rmii reception cycle timing (rtl8201e(l)-vb only) table 36. rmii reception cycle timing (rtl8201e(l)-vb only) symbol description minimum typical maximum unit t_ipsu_rxd_rmii rxd/crs_dv setup time to refclk 4 - - ns t_iphd_rxd_rmii rxd/crs_dv hold time from refclk 2 - - ns valid data refclk rxd t_ipsu_rxd_rmii t_iphd_rxd_rmii figure 14. rmii reception cycle timing
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 32 track id: jatr-1076-21 rev. 1.3 9.2.5. sni transmission cycle timing table 37. sni transmission cycle timing symbol description minimum maximum unit t 1 txclk high pulse width 36 - ns t 2 txclk low pulse width 36 - ns t 3 txclk period 80 120 ns t 4 txen, txd0 setup to txclk rising edge 20 - ns t 5 txen, txd0 hold after txclk rising edge 10 - ns t 8 transmit latency - 50 ns figure 15 and figure 16 show an example of a packet transfer from mac to phy on the sni interface. note: sni mode only runs at 10mbps. figure 15. sni transmission cycle timing-1 txclk txen txd0 tptx+- t 8 figure 16. sni transmission cycle timing-2
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 33 track id: jatr-1076-21 rev. 1.3 9.2.6. sni reception cycle timing table 38. sni reception cycle timing symbol description minimum typical maximum unit t 1 rxclk high pulse width 36 - - ns t 2 rxclk low pulse width 36 - - ns t 3 rxclk period 80 - 120 ns t 4 rxd0 setup to rxclk rising edge 40 - - ns t 5 rxd0 hold after rxclk rising edge 40 - - ns t 6 receive frame to crs high - - 50 ns t 7 end of receive frame to crs low - - 160 ns t 8 decoder acquisition time - 600 1800 ns figure 17 and figure 18 show an example of a packet transfer from phy to mac on the sni interface. note: sni mode only runs at 10mbps. figure 17. sni reception cycle timing-1 figure 18. sni reception cycle timing-2
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 34 track id: jatr-1076-21 rev. 1.3 9.2.7. mdc/mdio timing table 39. mdc/mdio timing symbol description minimum maximum unit t 1 mdc high pulse width 160 - ns t 2 mdc low pulse width 160 - ns t 3 mdc period 400 - ns t 4 mdio setup to mdc rising edge 10 - ns t 5 mdio hold time from mdc rising edge 10 - ns t 6 mdio valid from mdc rising edge 0 300 ns mdc mdio sourced by sta v ih(min) v il (max) v ih(min) v il (max) mdio sourced by rtl8201el v ih(min) v il(max) t 4 t 5 t 3 t 1 t 2 t 6 figure 19. mdc/mdio timing 9.2.8. transmission without collision figure 20 shows an example of a pack et transfer from mac to phy. figure 20. mac to phy transmission without collision
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 35 track id: jatr-1076-21 rev. 1.3 9.2.9. reception without error figure 21 shows an example of a pack et transfer from phy to mac. figure 21. phy to mac reception without error 9.3. crystal characteristics table 40. crystal characteristics parameter range nominal frequency 25.000mhz oscillation mode base wave frequency tolerance at 25 c 50ppm frequency tolerance at -20~70 c 30ppm operating temperature range -10 c ~ +70 c equivalent series resistance 30ohm max. drive level 0.1mv load capacitance 20pf shunt capacitance 7pf max. insulation resistance mega ohm min./dc 100v test impedance meter saunders 250a aging rate per year 0.0003% 9.4. transformer characteristics table 41. transformer characteristics parameter transmit end receive end turn ratio 1:1 ct 1:1 ct inductance (min.) 350h @ 8ma 350h @ 8ma
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 36 track id: jatr-1076-21 rev. 1.3 10. mechanical dimensions 10.1. rtl8201e (32-pin qfn) symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 3 0.20 ref 0.008 ref b 0.18 0.25 0.30 0.007 0.010 0.012 c - - 0.6 - - 0.024 d/e 5.00 bsc 0.197 bsc d 2 /e 2 3.10 3.35 3.60 0.122 0.132 0.142 e 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 note 1: controlling dime nsion: millimeter (mm). note 2: reference docu mentl: jedec mo-220.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 37 track id: jatr-1076-21 rev. 1.3 10.2. rtl8201el (48-pin lqfp) symbol dimension in mm dimension in inch min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 d/e 9.00 bsc 0.354 bsc d 1 /e 1 7.00 bsc 0.276 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref note 1: controlling dime nsion: millimeter (mm). note 2: reference docu mentl: jedec ms-026.
rtl8201e(l) datasheet single-chip/port 10/100 fast ethernet phyceiver with auto mdix 38 track id: jatr-1076-21 rev. 1.3 11. ordering information table 42. ordering information part number package status RTL8201E-GR 32-pin qfn with green package production rtl8201el-gr 48-pin lqfp with green package production rtl8201e-vb-gr RTL8201E-GR version b (adds rmii and intb support) sampling rtl8201el-vb-gr rtl8201el-gr version b (adds rmii and intb support) sampling note: see page 4 and 5 for package identification. realtek semiconductor corp. headquarters no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan. tel: 886-3-578-0211 fax: 886-3-577-6047 www.realtek.com

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